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CXP973F064
CMOS 16-bit Single Chip Microcomputer
Description The CXP973F064 is a CMOS 16-bit microcomputer integrating on a single chip an A/D converter, serial interface, I2C bus interface, timer, PWM output circuit, programmable pattern generator, remote control receive circuit, parallel interface, FLASH ROM interface, and as well as basic configurations like a 16-bit CPU, ROM, RAM, and I/O port. This LSI also provides the sleep/stop functions that enable lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic)
104 pin LFLGA (Plastic) Features * An efficient instruction set as a controller -- Direct addressing, numerous abbreviated forms, multiplication and division instructions * Instruction sets for C language and RTOS -- Highly quadratic instruction system, generalpurpose register of 16-bit x 8-pin x 16-bank configuration * Minimum instruction cycle 58.8ns at 34MHz operation (3.0 to 3.6V) 66.7ns at 30MHz operation (2.7 to 3.6V) * Incorporated EEPROM capacity 256K bytes * Incorporated RAM capacity 11.5K bytes * Peripheral functions -- A/D converter 8-bit 12-analog input, successive approximation system, 3-stage FIFO (Conversion time: 1.55s at 40MHz) -- Serial interface Asynchronous serial interface (UART) 128-byte buffer RAM, 3 channels -- I2C bus interface 64-byte buffer RAM (supports master/slave and automatic transfer mode) -- Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels, watchdog timer -- PWM output circuit 14-bit PWM, 4 channels (2-channel of binary output switch function by PPG) -- Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel -- Remote control receive circuit 8-bit pulse measurement counter, 10-stage FIFO -- Parallel interface External register interface (8-bit parallel bus), 4-chip select * Interruption * Standby mode * Package 33 factors, 33 vectors, multi-interruption and priority selection possible Sleep/stop 100-pin plastic QFP 100-pin plastic LQFP 104-pin plastic LFLGA CXP971000 CXP972032/973032/973064
* Piggy/evaluation chip * Mask ROM Structure Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99Z25B15-PS
Block Diagram
NMI INT0 to INT7 KS0 to KS19 PWE EXTAL XTAL RST VDD VSS
8 BUFFER RAM SPC970 CPU CORE PORT B 8 CLOCK GENERATOR/ SYSTEM CONTROLLER PORT A 8
20
SCS0 SI0 SO0 SCK0
SERIAL INTERFACE UNIT (CH0)
PA0 to PA7
PB0 to PB7
SCS1 SI1 SO1 SCK1 BUFFER RAM 2 3 2 BUFFER RAM 2 4 FLASH EEPROM 256K BYTES RAM 11.5K BYTES PORT C
SERIAL INTERFACE UNIT (CH1)
8
PC0 to PC7
INTERRUPT CONTROLLER
TxD RxD BUFFER RAM
UART PRESCALER/ TIME-BASE TIMER
PORT D
SCS2 SI2 SO2 SCK2
SERIAL INTERFACE UNIT (CH2)
8
PD0 to PD7
SCL SDA
I2C BUS INTERFACE UNIT
PORT E
8
PE0 to PE7
8-BIT TIMER/COUNTER (CH0)
T1
8-BIT TIMER (CH1)
PORT F
EC2 CINT T2 BUFFER RAM
16-BIT CAPTURE TIMER/COUNTER (CH2) FIFO
PORT G
4CH 16-BIT TIMER
PORT H
PWM3 PWM2
RMC
REMOCON FIFO
PORT J
PWM1 PWM0
2CH 14-BIT PWM (PPG)
PROGRAMABLE PATTEERN GENERATOR
A/D CONVERTER
EXT. REGISTERS INTERFACE
PORT I
16 PPO00 to PPO15
12 XCS3 XCS2 XCS1 XCS0 ADTEN ADTRG AVSS AVREF AVDD AN0 to AN11
16 A0 to A15
8 XRD XWR D0 to D7
PORT K
-2-
6 2 4 4 4 4
PF0 to PF5 PF6, PF7 PG0 to PG3 PG4 to PG7 PH0, PH1, PH6, PH7 PH2 to PH5
EC0
WATCHDOG TIMER
2CH 14-BIT PWM
8
PI0 to PI7
8
PJ0 to PJ7
5 2
PK0 to PK4 PK5 to PK6
CXP973F064
CXP973F064
Pin Assignment 1 (Top View) 100-pin QFP package
PB1/PPO01/A9 PB0/PPO00/A8
PH5/TETC
PH6/XWR
PH4/RMC
PH7/XRD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PH1/SCL
PH2/RxD
PH3/TxD
PA7/A7
PA6/A6
PA5/A5
PA4/A4
PA3/A3
PA2/A2
PA1/A1
PA0/A0
PWE
VDD
VSS
PB2/PPO02/A10 PB3/PPO03/A11 PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15 PC0/PPO08 PC1/PPO09 PC2/PPO10 PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0 VSS PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19 PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PE4/INT4 PE5/INT5 PE6/INT6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PH0/SDA PK6/TETA PK5/TETB PK4/ADTRG PK3/ADTEN PK2 PK1 PK0 AVDD AVREF AVSS PJ7/AN11/KS11 PJ6/AN10/KS10 PJ5/AN9/KS9 PJ4/AN8/KS8 PJ3/AN7/KS7 PJ2/AN6/KS6 PJ1/AN5/KS5 PJ0/AN4/KS4 PI7/AN3/KS3 PI6/AN2/KS2 PI5/AN1/KS1 PI4/AN0/KS0 Vss PI3/SCK2 PI2/SO2 PI1/SI2 PI0/SCS2 PG7/SCK0 PG6/SO0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PE7/INT7/CINT
PF2/SCS1/NMI
PF0/EC0
PF1/EC2
PF3/SI1
PF4/SO1
PF5/SCK1
PF6/T1
PF7/T2
RST
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/SCS0
Note) 1. PWE (Pin 88) must be connected to NC for Mask ROM. 2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND. 3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD. -3-
PG5/SI0
VSS
XTAL
EXTAL
VDD
CXP973F064
Pin Assignment 2 (Top View) 100-pin LQFP package
PB2/PPO02/A10
PB3/PPO03/A11
PB1/PPO01/A9
PB0/PPO00/A8
PH5/TETC
PH6/XWR
PH4/RMC
PH7/XRD
PA7/A7
PA6/A6
PA5/A5
PA4/A4
PA3/A3
PA2/A2
PA1/A1
PA0/A0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PK4/ADTRG PK3/ADTEN PK2 PK1 PK0 AVDD AVREF AVSS PJ7/AN11/KS11 PJ6/AN10/KS10 PJ5/AN9/KS9 PJ4/AN8/KS8 PJ3/AN7/KS7 PJ2/AN6/KS6 PJ1/AN5/KS5 PJ0/AN4/KS4 PI7/AN3/KS3 PI6/AN2/KS2 PI5/AN1/KS1 PI4/AN0/KS0 Vss PI3/SCK2 PI2/SO2 PI1/SI2 PI0/SCS2
PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15 PC0/PPO08 PC1/PPO09 PC2/PPO10 PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0 VSS PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19 PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
PH1/SCL
PH2/RxD
PH3/TxD
PWE
VDD
PK5/TETB 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PG7/SCK0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PF0/EC0
PF1/EC2
PF4/SO1
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PE7/INT7/CINT
PF2/SCS1/NMI
PG4/SCS0
PF5/SCK1
PG5/SI0
VSS
PF3/SI1
PF6/T1
PF7/T2
RST
XTAL
EXTAL
VDD
PE4/INT4
PE5/INT5
Note) 1. PWE (Pin 86) must be connected to NC for Mask ROM. 2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND. 3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD. -4-
PE6/INT6
PG6/SO0
PK6/TETA
PH0/SDA
CXP973F064
Pin Assignment 3 (Top View) 104-pin LFLGA package
1 A B C D E 2 PB5 5 PC0
2
3 97 PB0 99 PB2
4 95 PA6 96 PA7 98 PB1
5 92 PA3 93 PA4 94 PA5
6 90 PA1 91 PA2 89 PA0
7 87 VDD 88 VSS
8 84 PH6 85 PH7
9 82 PH4 81 PH3 79 PH1
10 80 PH2 76 PK5 78 PH0
11 77 PK6 75 PK4
12
13
100 PB3 1 PB4 6 PC1 9 PC4 13 VSS 16 PD2 18 PD4 21 PD7 24 PE2 25 PE3 27 PE5 3 PB6 4 PB7 8 PC3 11 PC6 14 PD0 19 PD5 23 PE1
86 83 PWE PH5
74 PK3
72 PK1
73 70 69 PK2 AVDD AVREF 71 68 PK0 AVSS 66 65 PJ6 PJ5 63 PJ3 58 PI6 54 PI3 53 PI2 28 PE6 26 PE4 29 PE7 30 PF0 32 PF2 31 PF1 33 PF3 35 PF5 34 PF4 36 41 46 PF6 EXTAL PG3 38 40 43 RST XTAL PG0 37 PF7 39 VSS 42 VDD 48 PG5 45 PG2 44 PG1 49 PG6 47 PG4 61 PJ1 60 PJ0 56 PI4 51 PI0 50 PG7 67 PJ7 64 PJ4 62 PJ2 59 PI7 57 PI5 55 VSS 52 PI1
7 PC2 F 10 PC5 G 12 PC7 H 15 PD1 J 17 PD3 K 20 PD6 L 22 PE0 M N
Note) 1. PWE (Pin C7) must be connected to NC for Mask ROM. 2. Vss and AVss (Pins B7, E12, G2, K13 and N8) must be connected to GND. 3. VDD and AVDD (Pins A7, D12 and N9) must be connected to VDD. -5-
CXP973F064
Pin Functions Symbol PA0/A0 to PA7/A7 I/O (Port A) Output / Output 8-bit output port. (8 pins) (Port B) 8-bit output port. PPO value and OR output. (8 pins) (Port C) 8-bit I/O port. I/O can be specified in 1-bit units. PPO value and OR output. (8 pins) (Port D) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins) (Port E) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins) Functions External register interface address bus port output data value and OR output. (8 pins) External register interface address bus. Address width can be extended in 1-bit units. (8 pins) Programmable pattern generator outputs. (16 pins) External register interface chip select signal. Chip select signal output function can be selected in 1-bit units. (4 pins) Standby release input function can be specified in 1-bit units. (8 pins)
PB0/PPO00/ Output / A8 to PB7/PPO07/ Output / Output A15 PC0/PPO08 I/O / Output to PC3/PPO11 PC4/PPO12/ I/O / Output / XCS3 to PC7/PPO15/ Output XCS0 PD0/D0/ KS12 to PD7/D7/ KS19 PE0/INT0 to PE6/INT6 PE7/INT7/ CINT PF0/EC0 PF1/EC2 PF2/SCS1/ NMI PF3/SI1 PF4/SO1 PF5/SCK1 PF6/T1 PF7/T2
I/O / I/O / Input
External register interface data bus. (8 pins) External interrupt inputs. (8 pins)
I/O / Input I/O / Input / Input Input / Input Input / Input / Input Input / Input Input / Output Input / I/O Output / Output Output / Output
External capture input for 16-bit capture timer/counter. External event inputs for 8-bit timer/counter. (2 pins) Serial chip select (CH1) input. Serial data (CH1) input. Serial data (CH1) output. Serial clock (CH1) I/O. 8-bit timer/counter output. 16-bit capture timer/counter timing output. 14-bit PWM output with output value switch control by programmable pattern generator. (2 pins) 14-bit PWM output. (2 pins) Serial chip select (CH0) input. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH0) I/O. Non-maskable external interrupt input.
(Port F) 8-bit port. Lower 6 bits are for input; upper 2 bits are for output. (8 pins)
PG0/PWM0 Output / Output to PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/SCS0 PG5/SI0 PG6/SO0 PG7/SCK0 (Port G) 8-bit port. Lower 4 bits Output / Output are for output; upper 4 bits are for I/O. Upper I/O / Input 4 bits can be specified I/O / Input in 1-bit units. (8 pins) I/O / Output I/O / I/O
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CXP973F064
Symbol PH0/SDA PH1/SCL PH2/RxD
I/O Output / I/O Output / I/O I/O / Input (Port H) 8-bit port. Lower 2 bits are for large current N-ch open drain outputs; medium 4 bits are for I/O; upper 2 bits are for output. Medium 4 bits can be specified in 1-bit units. (8 pins) I2C
Functions bus interface data I/O.
I2C bus interface clock I/O. UART reception data input. (common with data reception during on-board rewrite boot mode) UART transmission data output. (common with data transmission during on-board rewrite boot mode) Remote control signal input. On-board rewrite boot mode setting. (Total 3 pins) External register interface write signal. External register interface read signal. Serial chip select (CH2) input. Serial data (CH2) input. (Port I) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins) Serial data (CH2) output. Serial clock (CH2) I/O.
PH3/TxD PH4/RMC PH5/TETC PH6/XWR PH7/XRD PI0/SCS2 PI1/SI2 PI2/SO2 PI3/SCK2 PI4/AN0/ KS0 to PI7/AN3/ KS3 PJ0/AN4/ KS4 to PJ7/AN11/ KS11 PK0 to PK2 PK3/ADTEN PK4/ADTRG PK5/TETB PK6/TETA EXTAL XTAL RST AVDD AVREF AVss VDD Vss PWE
I/O / Output I/O / Input I/O / Input Output / Output Output / Output I/O / Input I/O / Input I/O / Output I/O / I/O I/O / Input / Input
I/O / Input / Input
(Port J) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins) (Port K) 7-bit port. Lower 5 bits are for I/O; upper 2 bits are for output. Lower 5 bits can be specified in 1-bit units. (7 pins)
Analog input for A/D converter. (12 pins)
Standby release input function can be specified in 1-bit units. (12 pins)
I/O I/O / Input I/O / Input Output / Input Output / Input Input
A/D converter operation enable input by external trigger. External trigger input for A/D converter. On-board rewrite boot mode setting. (Total 3 pins)
Connects a crystal for main clock oscillation. (When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL.) System reset. Active at "L" level. Positive power supply for A/D converter. (Must be the same voltage with VDD.)
Input
Input
Reference voltage input for A/D converter. (Must be the same voltage with VDD.) GND for A/D converter. Positive power supply. (Connect both VDD pins to positive power supply.) GND (Connect all four Vss pins to GND.)
Input
FLASH EEPROM rewrite enable. -7-
CXP973F064
I/O Circuit Format for Pins Pin Circuit format After a reset
A0 to A7 PA register
PA0/A0 to PA7/A7
(Undefined after a reset) Internal data bus RD PA register write Reset S R Q
Hi-Z
Address width setting ("0" after a reset) A8 to A15 1 MPX 0
PB0/PPO00/A8 to PB7/PPO07/ A15
PPO00 to PPO07 PB register
Hi-Z
(Undefined after a reset) Internal data bus PB register write RD Reset
S R
Q
PPO08 to PPO11 PC register ("0" after a reset)
PC0/PPO08 to PC3/PPO11
PCD register ("0" after a reset) Internal data bus RD
Input IP protection circuit
Hi-Z
-8-
CXP973F064
Pin
XCS output setting ("0" after a reset) XCS3 to XCS0 PPO12 to PPO15
Circuit format
After a reset
1 MPX 0
PC4/PPO12/ XCS3 to PC7/PPO15/ XCS0
PC register ("0" after a reset) PCD register ("0" after a reset) Internal data bus RD IP
Hi-Z
WR (external register area) Internal data bus External register I/F
External register operation enable CLR PD register ("0" after a reset) CLR PDD register ("0" after a reset)
IP
PD0/D0/KS12 to PD7/D7/ KS19
Hi-Z
Internal data bus RD Standby release Internal data bus External register I/F External register operation enable RD (external register area)
Large current drive 5mA (VDD = 2.7 to 3.6V)
PE register (Undefined after a reset)
PE0/INT0 to PE7/INT7/ CINT
Internal data bus
PED register ("0" after a reset)
IP
Hi-Z
RD INT0 to INT7/CINT CMOS Schmitt input
-9-
CXP973F064
Pin
Circuit format
After a reset
EC0, EC2
IP CMOS Schmitt input
PF0/EC0 PF1/EC2
Hi-Z
Internal data bus RD
Internal data bus RD CMOS Schmitt input
IP
PF2/SCS1/ NMI
SCS1
PFSL register ("0" after a reset)
Hi-Z
NMI
NMI input enable ("0" after a reset)
Internal data bus
IP RD CMOS Schmitt input PFSL register ("0" after a reset)
PF3/SI1
SI1
Hi-Z
SO1 SO1 output enable
PF4/SO1
PFSL register ("0" after a reset) Internal data bus RD
Hi-Z
IP
SCK1 SCK1 output enable
PF5/SCK1
PFSL register ("0" after a reset) Internal data bus RD SCK1
Hi-Z
IP
CMOS Schmitt input
- 10 -
CXP973F064
Pin
Circuit format
After a reset
T1 PF register
1 MPX 0
PF6/T1
("1" after a reset) PFSL register ("0" after a reset) Internal data bus RD
"H" level
T2 PF register ("1" after a reset)
1 MPX 0
PF7/T2
PFSL register ("0" after a reset) Internal data bus RD PF register write Reset S R Q
Pull-up
"H" level ("H" level at ON resistance of pull-up transistor by a reset.)
transistor approximately 150k (VDD = 2.7 to 3.6V)
PWM0 to PWM3 PG register (Undefined after a reset)
1 MPX 0
PG0/PWM0 to PG3/PWM3
PGSL register ("0" after a reset) Internal data bus RD PG register write Reset S R Q
Hi-Z
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CXP973F064
Pin
Circuit format
PG register (Undefined after a reset) PGD register ("0" after a reset)
After a reset
PG4/SCS0
SCS0
PGSL register ("0" after a reset) IP
Hi-Z
Internal data bus RD CMOS Schmitt input
PG register (Undefined after a reset) PGD register ("0" after a reset)
PG5/SI0
SI0
PGSL register ("0" after a reset) IP
Hi-Z
Internal data bus RD CMOS Schmitt input
SO0 PG register (Undefined after a reset) PGSL register ("0" after a reset)
1 MPX 0
PG6/SO0
IP 1 MPX 0
SO0 output enable PGD register ("0" after a reset) Internal data bus RD
Hi-Z
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CXP973F064
Pin
SCK0 PG register
Circuit format
1 MPX 0
After a reset
(Undefined after a reset) PGSL register ("0" after a reset) IP 1 MPX 0
PG7/SCK0
SCK0 output enable PGD register ("0" after a reset) Internal data bus RD SCK0
Hi-Z
CMOS Schmitt input
SDA, SCL PH register ("1" after a reset) PHSL register
1 MPX 0
PH0/SDA PH1/SCL
("0" after a reset) Internal data bus SDA, SCL RD CMOS Schmitt input
IP
Hi-Z
Large current drive 5mA (VDD = 2.7 to 3.6V)
PHL register (Undefined after a reset) PHD register IP
PH2/RxD
Internal data bus
("0" after a reset)
Hi-Z
RD RxD CMOS Schmitt input
- 13 -
CXP973F064
Pin
TxD PH register
Circuit format
1 MPX 0
After a reset
(Undefined after a reset) TxD output enable
PH3/TxD
PHD register ("0" after a reset) Internal data bus RD IP
Hi-Z
PH register (Undefined after a reset)
PH4/RMC
PHD register ("0" after a reset)
IP
Hi-Z
Internal data bus RD RMC CMOS Schmitt input
PH register (Undefined after a reset)
PH5/TETC
PHD register ("0" after a reset)
IP
Hi-Z
Internal data bus RD CMOS Schmitt input
PHSL register ("0" after a reset) XWR, XRD 1 MPX 0
PH6/XWR PH7/XRD
PH register (Undefined after a reset) Internal data bus RD
Hi-Z
PH register write Reset
S R
Q
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CXP973F064
Pin
PI register
Circuit format
After a reset
(Undefined after a reset) PID register ("0" after a reset)
PI0/SCS2
SCS2
PISL register ("0" after a reset) IP
Hi-Z
Internal data bus RD CMOS Schmitt input
PI register (Undefined after a reset) PID register ("0" after a reset)
PI1/SI2
SI2
PISL register ("0" after a reset) IP
Hi-Z
Internal data bus RD CMOS Schmitt input
SO2 PI register (Undefined after a reset) PISL register ("0" after a reset)
1 MPX 0
PI2/SO2
IP 1 MPX 0
SO2 output enable PID register ("0" after a reset) Internal data bus RD
Hi-Z
- 15 -
CXP973F064
Pin
SCK2 PI register
Circuit format
1 MPX 0
After a reset
(Undefined after a reset) PISL register ("0" after a reset) IP 1 MPX 0
PI3/SCK2
SCK2 output enable PID register ("0" after a reset)
Hi-Z
Internal data bus RD SCK2 CMOS Schmitt input
PI register (Undefined after a reset) PID register ("0" after a reset)
PI4/AN0/KS0 to PI7/AN3/ KS3
Internal data bus
PISL register ("0" after a reset) IP
Hi-Z
RD Standby release A/D converter Input multiplexer
PJ register (Undefined after a reset) PJD register ("0" after a reset)
PJ0/AN4/KS4 to PJ7/AN11/ KS11
Internal data bus
PJSL register ("0" after a reset) IP
Hi-Z
RD Standby release A/D converter Input multiplexer
- 16 -
CXP973F064
Pin
Circuit format
After a reset
PK register (Undefined after a reset)
PK0 to PK2
PKD register ("0" after a reset)
IP
Hi-Z
Internal data bus RD
PK register (Undefined after a reset)
PK3/ADTEN PK4/ADTRG
Internal data bus
PKD register ("0" after a reset)
IP
Hi-Z
RD ADTEN, ADTRG CMOS Schmitt input
PK register
PK5/TETB
("1" after a reset) Internal data bus RD
"H" level
PK register ("1" after a reset)
PK6/TETA
Internal data bus RD PK register write Reset S R Q
Pull-up
"H" level ("H" level at ON resistance of pull-up transistor by a reset.)
transistor approximately 150k (VDD = 2.7 to 3.6V)
- 17 -
CXP973F064
Pin
Circuit format
After a reset
EXTAL
IP
Timing generator
XTAL EXTAL
Oscillation stop control
Oscillation
XTAL * Diagram shows circuit configuration during oscillation. * Feedback resistor is reoved during standby stop mode, and XTAL is driven at "H" level.
Mask option
OP
RST
RST
IP CMOS Schmitt input
Pull-up
Internal reset circuit
"L" level (during a reset)
transistor approximately 30k (VDD = 2.7 to 3.6V)
PWE
PWE
IP
FLASH EEPROM
Hi-Z
- 18 -
CXP973F064
Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVREF AVSS Input voltage Output voltage High level output current High level total output current VIN VOUT IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature IOL Topr Tstg 20.0 130 -30 to +85 -55 to +150 600 Allowable power dissipation PD 380 500 mW mA mA C C Rating -0.3 to +4.6 AVSS to +4.61 AVSS to +4.61 -0.3 to +0.3 -0.3 to +4.62 -0.3 to +4.62 -5.0 -50 15.0 Unit V V V V V V mA mA mA
(Vss = 0V reference) Remarks
Output (value per pin) Total for all output pins All pins excluding large current output pins (value per pin) Large current output pins3 (value per pin) Total for all output pins
QFP-100P-L01 LQFP-100P-L01 LFLGA-104P-01
1 AVDD and AVREF must be the same voltage with VDD. 2 VIN and VOUT excluding PH0 and PH1 must not exceed VDD + 0.3V. 3 The large current drive transistor is N-ch transistor of PD and PH0, PH1. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
- 19 -
CXP973F064
Recommended Operating Conditions Item Symbol VDD Supply voltage AVDD AVREF VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr Tpwe Min. 2.7 2.0 2.7 2.7 0.7VDD 0.8VDD Max. 3.6 3.6 3.6 3.6 VDD VDD Unit V V V V V V V V V C C CMOS Schmitt input3 EXTAL4 Remarks
(Vss = 0V reference)
Guaranteed data hold range during stop mode 1 1 2 CMOS Schmitt input3 EXTAL4
VDD - 0.4 VDD + 0.2 0 0 -0.3 -30 0 0.2VDD 0.2VDD 0.4 +85 +50
Recommended operating range of FLASH EEPROM rewrite operation
1 AVDD and AVREF must be the same voltage with VDD. 2 PC, PD, PF4, PG6, PH3, PI2, PI4 to PI7, PJ, PK0 to PK2, PWE for normal input port. 3 RST, PE, PF0 to PF3, PF5, PG4, PG5, PG7, PH0 to PH2, PH4, PH5, PI0, PI1, PI3, PK3 and PK4. 4 Specified only during self-oscillation.
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CXP973F064
Electrical Characteristics DC Characteristics 1 Item Symbol Pins PD to PE, PF6, PF7, PG0 to PG5, PH2, PH4, PH5, PI to PJ, PK0 to PK6 PA to PC, PF4, PF5, PG6, PG7, PH3, PH6, PH7, PI2, PI3 Conditions VDD = 3.0V, IOH = -0.15mA VDD = 2.7V, IOH = -0.15mA VDD = 3.0V, IOH = -0.5mA VDD = 2.7V, IOH = -0.5mA VDD = 3.0V, IOH = -1.5mA VDD = 2.7V, IOH = -1.5mA (Topr = -30 to +85C, Vss = 0V reference) Min. 2.70 2.40 2.30 2.00 2.30 V 2.00 0.30 0.50 0.30 0.50 1.00 0.3 -0.3 -0.9 61 -61 -250 31 V V V V V A A A A V V Typ. Max. Unit
High level output voltage
VOH
Low level output voltage
PE, PF6, PF7, IOL = 1.2mA PG0 to PG5, PH2, PH4, PH5, PI0, PI1, PI4 to PI7, IOL = 1.6mA PJ, PK0 to PK6 VOL PA to PC, PF4, PF5, PG6, PG7, PH3, PH6, PH7, PI2, PI3 PD, PH0, PH1 IIHE IOL = 2.0mA IOL = 3.0mA IOL = 5.0mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL = 0.3V
Input current
IILE IILR
EXTAL RST1
I/O leakage IIZ current Open drain output leakage current (N-ch Tr. off-state)
PA to PJ, PK0 to PK6, VDD = 3.6V, VI = 0, 3.6V RST1
ILOH
PH0, PH1
VDD = 3.6V, VIH = 3.6V
31
A
1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected.
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CXP973F064
DC Characteristics 2 Item Symbol 2 IDD1 Pins VDD, VSS Conditions
(Topr = -30 to +85C, Vss = 0V reference) Min. Typ. 50 Max. 57 Unit mA
VDD = 3.3 0.3V, fEX = fsrc = 40MHz, External clock operation A/D off state, PLL off state VDD = 3.3 0.3V, fEX = fsrc = 40MHz, External clock operation A/D off state, PLL off state, sleep mode 85C or less
Supply current1
2 IDDS2
VDD, VSS
20
23
mA
500 300 80 A
IDDS3
VDD, VSS
VDD = 3.6V, stop mode
75C or less 50C or less
1 When all output pins are open. 2 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (1/2 frequency dividing clock).
I/O Capacitance Item Input capacitance Symbol CIN Pins PF0 to PF3, EXTAL, RST Conditions Clock 1MHz, 0V for all pins excluding measured pins Min. Typ. 10 Max. 20 Unit pF
Output capacitance
COUT
PA to PB, PF6, PF7, Clock 1MHz, PG0 to PG3, 0V for all pins excluding PH6, PH7, PK5, PK6, measured pins XTAL PC to PE, PF4, PF5, Clock 1MHz, PG4 to PG7, 0V for all pins excluding PH0 to PH5, PI to PJ, measured pins PK0 to PK4
10
20
pF
I/O capacitance
CI/O
10
20
pF
- 22 -
CXP973F064
AC Characteristics (1) Clock timing Item Symbol Pins Fig.1, Fig.2 Main clock base oscillation frequency EXTAL, XTAL Fig.1, Fig.2 -30 to +75C Fig.1, Fig.2 -30 to +50C (Topr = -30 to +85C, VDD = 2.7 to 3.6 V, Vss = 0V reference) Conditions VDD = 3.3 0.3V VDD = 3.0 0.3V fEX VDD = 3.3 0.3V VDD = 3.0 0.3V VDD = 3.3 0.3V VDD = 3.0 0.3V Min. Typ. Max. Unit 9.5 9.5 9.5 9.5 9.5 9.5 4.0 34.5 31.0 35.5 32.5 38.5 35.0 MHz
MHz
MHz
tXH tXL
Main clock base oscillation input pulse width
fEX = 40.0MHz Fig.1, Fig.2 External clock drive EXTAL, XTAL fEX = 33.86MHz Fig.1, Fig.2 External clock drive fEX = 20.0MHz Fig.1, Fig.2 External clock drive fEX = 40.0MHz Fig.1, Fig.2 External clock drive EXTAL, XTAL fEX = 33.86MHz Fig.1, Fig.2 External clock drive fEX = 20.0MHz Fig.1, Fig.2 External clock drive XTAL Fig.1, Fig.2 1/2 VDD point
ns
tXH tXL tXH tXL tXR tXF
4.0
ns
11
ns
8.5
ns
Main clock base oscillation input rise time, fall time
tXR tXF tXR tXF
10.5
ns
14
ns
Main clock duty Note)
duty
40
50
60
%
tsys indicates the four values below according to the upper two bits (PCK1, PCK0) of the clock control
register (CLC: 0002FEh). tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10, 16/fEX (PCK1, PCK0 = 11)
- 23 -
CXP973F064
1/fEX
EXTAL XTAL
VDD - 0.4V 0.4V
tXH
tXF tEX
tXL
tXR
XTAL
1/2VDD
tX duty = tx/tEX; tEX = 1/fEX
Fig. 1. Clock timing
Oscillator connection example of main oscillation circuit
Connection example (1) of external clock
Connection example (2) of external clock
EXTAL
XTAL
EXTAL
XTAL
EXTAL
XTAL
(i)
(ii)
(iii)
Fig. 2. Oscillator connection and clock applied conditions
- 24 -
CXP973F064
(2) Event count input Item Event count input clock pulse width Symbol Pins EC0, EC2
(Topr = -30 to +85C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions Fig. 3 Min. Max. Unit ns
tEH, tEL
tsys + 100
0.8VDD EC0 EC2 0.2VDD
tEH
tEL
Fig. 3. Event count input timing
(3) Interruption and reset input Item Symbol Pins
(Topr = -30 to +85C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions Main mode Sleep mode Fig. 4 Noise filter selected Fig. 4 Fig. 5 PS4 PS6 Min. Max. Unit
External interruption high, low level width
tIH, tIL
NMI, INT0 to INT7, KS0 to KS19
tsys + 100
2tsys + 100 32/fEX + 100 128/fEX + 100 50/fEX ns ns
INT4 to INT7
Reset input low level width
tRST
RST
tIH 0.8VDD NMI INT0 to INT7 KS0 to KS19
tIL
0.2VDD
Fig. 4. Interruption input timing
tRST
RST 0.2VDD
Fig. 5. Reset input timing
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CXP973F064
(4) A/D converter characteristics (Topr = -30 to +85C, VDD = AVDD = AVREF = 2.7 to 3.6V, Vss = AVss = 0V reference) Item Resolution Linearity error Absolute error Conversion time VDD = AVDD = AVREF = 3.0V 34tsys 1 1 AVREF AN0 to AN11 Main mode AVREF IREFS VDD = 3.3 0.3V fSRC = 40MHz VDD = 3.3 0.3V fSRC = 20MHz VDD = AVDD = AVREF 62tsys 10tsys 20tsys 2.7 0 1.5 1.2 3.6 AVREF 2.1 1.7 12 Symbol Pins Conditions Min. Typ. Max. Unit 8 1 3 Bits LSB LSB ns ns ns ns V V mA mA A
tCONV tSAMP
Sampling time
Reference input voltage VREF Analog input voltage
IREF AVREF current
ADC off state2 Stop mode
1 When Bit 6 (ADCK) of A/D control status register (ADCS: 000132h) is specified to "1". 2 When Bit 5 (ADPC) of A/D control status register (ADCS: 000132h) is specified to "1". Note) AVDD and AVREF must be the same voltage with VDD.
FFh FEh Digital conversion value
(100h) FFh FEh Digital conversion value
Linearity error
Absolute error 01h 00h Absolute error Analog input AVREF
01h 00h
VZT1
Analog input
VFT2
1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. 2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Fig. 6. Definition of A/D converter terms
- 26 -
CXP973F064
(5) Serial transfer (CH0, CH1, CH2) Item CS SCK delay time CS SCK float delay time CS SO delay time CS SO float delay time CS high level width Symbol Pins SCK0, SCK1, SCK2 SCK0, SCK1, SCK2 SO0, SO1, SO2 SCS0, SCS2
(Topr = -30 to +85C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions VDD = 3.3 0.3V External start transfer mode (SCK = output mode) VDD = 3.0 0.3V VDD = 3.3 0.3V VDD = 3.0 0.3V VDD = 3.3 0.3V VDD = 3.0 0.3V VDD = 3.3 0.3V VDD = 3.0 0.3V VDD = 3.3 0.3V VDD = 3.0 0.3V VDD = 3.3 0.3V Input mode Min. Max. 1.5tsys + 200 1.5tsys + 210 1.5tsys + 200 1.5tsys + 210 1.5tsys + 200 1.5tsys + 210 1.5tsys + 200 1.5tsys + 210 ns ns ns Unit ns
tDCSK
tDSKF
tDCSO
tDCSOF SCS1, External start transfer mode tWHCS
SCS0, SCS1, SCS2 SCK0, SCK1, SCK2
tsys + 100 tsys + 110
2tsys + 200 2tsys + 210 16/fEX 16/fEX
ns
ns
SCK cycle time
tKCY
VDD = 3.0 0.3V VDD = 3.3 0.3V
Output mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
SCK high, low pulse width
tKH, tKL
SCK0, SCK1, SCK2
Input mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
tsys + 100 tsys + 110
8/fEX - 100 8/fEX - 110 100 110 200 210 2tsys + 100 2tsys + 110 100 110 2tsys + 150 2tsys + 160 100 110 3tsys + 100 3tsys + 110 8/fEX - 100 8/fEX - 110
ns
ns
Output mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SI input data setup time (for SCK )
tSIK
SI0, SI1, SI2
SCK input mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SCK output mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SI input data hold time (for SCK )
tKSI
SI0, SI1, SI2
SCK input mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SCK output mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SCK SO delay time
tKSO
SO0, SO1, SO2
SCK input mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SCK output mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
Minimum interval time
tINT
SCK0, SCK1, SCK2
SCK input mode
VDD = 3.0 0.3V VDD = 3.3 0.3V
ns
SCK output mode
VDD = 3.0 0.3V
Note) The load condition for the SCK output mode and SO output delay time is 100pF. - 27 -
CXP973F064
tWHCS
0.8VDD SCS0 SCS1 SCS2 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 SCK1 SCK2 0.2VDD
tSIK
tKSI
0.8VDD SI0 SI1 SI2 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 SO1 SO2 Output data 0.2VDD
tINT
SCK0 SCK1 SCK2
0.8VDD
Fig. 7. Serial transfer CH0, CH1, CH2 timing - 28 -
CXP973F064
(6) I2C bus Item SCK clock frequency Bus free time between stop and start conditions Hold time under (resend) start condition Hold time in SCL clock low state Hold time in SCL clock high state Setup time under (resend) start condition Data hold time Data setup time SCL, SDA signal output rise time SCL, SDA signal output fall time Setup time under stop condition Symbol Pins SCL SDA SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL
(Topr = -30 to +85C, VDD = 2.7 to 3.6V, Vss = 0V reference) Standard mode Min. Max. 100 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 4.0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 1 20 + 1 0.6 300 300 0.9 High-speed mode Min. Max. 400 Unit kHz s s s s s s ns ns ns s
tSCL tBUF tHD;STA tLow tHigh tSU;STA tHD;DAT tSU;DAT tRd, tRc tFd, tFc tSU;STO
1 Due to the total capacitance of the bus.
tBUF
tSU;DAT
SDA tHD;STA tRd tFd tSCL tRc tLow tFc
SCL
tHD;STA
tHD;DAT
tHigh
tSU;STA
tSU;STO
Fig. 8. I2C bus timing - 29 -
CXP973F064
(7) Remote control reception Item Remote control receive high, low level width Symbol Pins
(Topr = -30 to +85C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions PS5 selected Typ. 128/fEX + 100 512/fEX + 100 2048/fEX + 100 ns Max. Unit
tRMC
RMC
Main mode
PS7 selected PS9 selected
0.8VDD RMC 0.2VDD
tRMC
tRMC
Fig. 9. Remote control signal input timing
- 30 -
CXP973F064
(8) External register interface
(Vss = 0V reference)
Item Chip select pulse width 1 Chip select pulse width 2 Chip select pulse width 3 Chip select pulse width 4 Chip select pulse width 5 Chip select pulse width 6 Chip select pulse width 7 Read/write strobe pulse width 1 Read/write strobe pulse width 2 Read/write strobe pulse width 3 Address setting time 1 Address setting time 2 Address hold time Read data setting request time Read data hold request time Write data setting time 1 Write data setting time 2 Write data hold time
3.3 0.3V 3.3 0.3V 3.0 0.3V Topr = -20 to +75C Topr = -30 to +85C Topr = -30 to +85C Symbol Min. Max. 1.5tsys 16.5tsys 32.5tsys 33.5tsys 17.5tsys 18.5tsys 34.5tsys Min. 1.5tsys -20 2.5tsys -20 2.5tsys -20 3.5tsys -20 2.5tsys -20 3.5tsys -20 4.5tsys -20 Max. 1.5tsys 16.5tsys 32.5tsys 33.5tsys 17.5tsys 18.5tsys 34.5tsys Min. 1.5tsys -30 2.5tsys -30 2.5tsys -30 3.5tsys -30 2.5tsys -30 3.5tsys -30 4.5tsys -30 Max. 1.5tsys 16.5tsys 32.5tsys 33.5tsys 17.5tsys 18.5tsys 34.5tsys
Unit
tCS1 tCS2 tCS3 tCS4 tCS5 tCS6 tCS7 tRW1 tRW2 tRW3 tAS1 tAS2 tAH tDS1 tDH1 tDS2 tDS3 tDH2
1.5tsys -20 2.5tsys -20 2.5tsys -20 3.5tsys -20 2.5tsys -20 3.5tsys -20 4.5tsys -20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsys - 25
2tsys - 25 2tsys - 25
tsys
16tsys 32tsys
tsys - 25
2tsys - 25 2tsys - 25
tsys
16tsys 32tsys
tsys - 35
2tsys - 35 2tsys - 35
tsys
16tsys 32tsys
tsys/2
-25 1.5tsys -25
tsys/2
1.5tsys -- -- -- 1.5tsys 16.5tsys
tsys/2
-25 1.5tsys -25
tsys/2
1.5tsys -- -- -- 1.5tsys 16.5tsys
tsys/2
-35 1.5tsys -35
tsys/2
1.5tsys -- -- -- 1.5tsys 16.5tsys
tsys/2
-25 15 0 1.5tsys -25 2.5tsys -25
tsys/2
-25 15 0 1.5tsys -25 2.5tsys -25
tsys/2
-35 20 0 1.5tsys -35 2.5tsys -35
tsys/2
-25
tsys/2
+30
tsys/2
-25
tsys/2
+30
tsys/2
-35
tsys/2
+30
- 31 -
CXP973F064
Read Timing
t1
t2
A15 to A0
tCS1 XCS3 to XCS0
tAH
tAS1
tRW1
XRD
tDS1 D7 to D0
tDH1
Fig. 10. Byte read (without programmable wait)
t1
t2 or tw
t3 or tW + 1
A15 to A0
tCS2 XCS3 to XCS0
tAH
tAS1
tRW2
XRD
tDS1 D7 to D0
tDH1
Fig. 11. Byte read (with programmable wait)
- 32 -
CXP973F064
t1
t2
t3
A15 to A0
EVEN ADD.
ODD ADD.
tCS3
tAH
XCS3 to XCS0 tAS1 tRW3
XRD tDS1 tDS1 tDH1
D7 to D0
Fig. 12. Word read (no strobe mode, without programmable wait)
t1
t2
t3
t4
A15 to A0
EVEN ADD.
ODD ADD.
tCS4
tAH
XCS3 to XCS0 tAS1 tRW1 tAH tAS1 tRW1
XRD tDS1 tDH1 tDS1 tDH1
D7 to D0
Fig. 13. Word read (strobe mode, without programmable wait)
- 33 -
CXP973F064
Write Timing
t1
t2
t3
A15 to A0
tCS5 XCS3 to XCS0
tAH
tAS2
tRW1
XWR
tDS2 D7 to D0
tDH2
Fig. 14. Byte write (without programmable wait)
t1
t2
t3 or tw
t4 or tW + 1
A15 to A0
tCS6 XCS3 to XCS0
tAH
tAS2
tRW2
XWR
tDS3 D7 to D0
tDH2
Fig. 15. Byte write (with programmable wait)
- 34 -
CXP973F064
t1
t2
t3
t4
t5
A15 to A0
EVEN ADD.
ODD ADD.
tCS7
tAH
XCS3 to XCS0 tRW1 tAH tAS1 tRW1
XWR tDS2 tDH2 tDS2 tDH2
D7 to D0
Fig. 16. Word write (without programmable wait)
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CXP973F064
Appendix SPC970 Series recommended oscillation circuit and oscillator
(i) Main oscillation circuit (ii) Main oscillation circuit (iii) Main oscillation circuit
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL
XTAL Rd
C1
C2 C1 C2
C1 C3
C2 L
Fig. 17. Recommended oscillation circuit
Manufacturer
Model CSA6.00MG040 CSA8.00MTZ CSA10.0MTZ CSA12.0MTZ CSA16.00MXZ040
fEX (MHz) 6.0 8.0 10.0 12.0 16.0 20.0 24.0 6.0 8.0 10.0 12.0 16.0 6.0
C1 (pF) 100 30 30 30 15 10 7 100 30 30 30 15 18 15 10 10
C2 (pF) 100 30 30 30 15 10 7 100 30 30 30 15 18 15 10 10
Rd () 0 0 0 0 0 0 0 0 0 0 0 0 560 330 330 220
Circuit example
Remarks
(i)
MURATA MFG CO., LTD.
CSA20.00MXZ040 CSA24.00MXZ040 CST6.00MGW040 CST8.00MTW CST10.0MTW CST12.0MTW CST16.00MXW0C3
(ii)
CL = 13.5pF (i) CL = 12pF CL = 9.5pF CL = 10pF CL: Load capacitor
RIVER ELETEC HC-49/U03 CO., LTD.
8.0 10.0 12.0
Indicates types with on-chip grounding capacitor (C1, C2).
- 36 -
CXP973F064
Manufacturer
Model
fEX (MHz) 6.0 8.0 10.0
C1 (pF) 15 15 10 12 12 12 12 1 3 3 1
C2 (pF) 15 15 10 12 12 12 12 1 0.01F 0.01F 0.01F
Rd () 5.6k 3.0k 1.8k 1.0k 470 390 200 100 0 0 0 0 0 0 0 0
Circuit example
Remarks CL = 16pF
HC-49/U-S
12.0 16.0 20.0
(i) CL = 12pF
KINSEKI LTD.
24.0 28.0 32.0 HC-49/U 36.0 40.0 CCR6.0MC5 CCR12.0MSC5 6.0 12.0 16.0 28.0 40.0
C3 = 10pF, L = 2.7H (iii) C3 = 5pF, L = 2.7H C3 = 3pF, L = 3.3H
36 (20%) 36 (20%) 20 (20%) 20 (20%) 10 (20%) 10 (20%) 10 (20%) 10 (20%) 5 5
TDK Corporation
CCR16.0MSC6 CCR28.0MSC6 CCR40.0MS6
(ii)
(i)
Indicates types with on-chip grounding capacitor (C1, C2).
CCR: Surface mounted type ceramic oscillator CL: Load capacitor
Product List Type Product name ROM capacitance RAM capacitance Package Main clock base oscillation frequency Reset pin pull-up resistor Flash EEPROM incorporated version CXP973F064Q-1, CXP973F064R-1, CXP973F064GA-1 256K byte 11.5K byte 100-pin plastic QFP, 100-pin plastic LQFP, 104-pin plastic LFLGA 40MHz Existent
- 37 -
CXP973F064
Notes on PK6 Usage FLASH EEPROM incorporated PK6 is also used as flash mode setting function. Note the followings: 1. "H" is output to PK6 during a reset. That is driven at comparatively high impedance (approximately 150k), and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load impedance. 2. When using software reset functions, PK6 may not rise enough during a reset. Switching PK6 to "H" output prior to software reset execution or connecting pull-up resistor is recommended.
RST Normal operation
PK6 Flash mode Keep PK6 above 0.7VDD during this period.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that FLASH EEPROM incorporated type is used, above countermeasure should be performed.
Limits on Usage of FLASH EEPROM incorporated Type The main clock doubler circuit is not guaranteed to operate.
- 38 -
CXP973F064
Characteristics Curve
IDD vs. VDD
(fEX = 40MHz, Topr = 25C, Typical) 60 54 48 IDD - Supply current [mA] 1/2 frequency 42 dividing mode 36 30 1/4 frequency dividing mode 24 1/8 frequency dividing mode 18 1/16 frequency dividing mode 12 6 0 2.1 2.4 2.7 3 3.3 3.6 3.9 IDD - Supply current [mA] 60 54 48 42 36 30 24 18 12 6 0 VDD - Supply voltage [V] 2.1
IDD vs. VDD
(fEX = 40MHz, Topr = 25C, Typical)
Sleep mode (1/2 frequency dividing mode) Sleep mode (1/4 frequency dividing mode) Sleep mode (1/8 frequency dividing mode) Sleep mode (1/16 frequency dividing mode)
2.4
2.7 3 3.3 3.6 VDD - Supply voltage [V]
3.9
IDD vs. fEX
(VDD = 3V, Topr = 25C, Typical) 60 54 48 IDD - Supply current [mA] 42 36 30 24 18 12 6 0 10 20 30 40 0 fEX - Main clock base oscillation frequency [MHz] 1/4 frequency dividing mode 1/8 frequency dividing mode 1/16 frequency dividing mode 1/2 frequency dividing mode 60 54 48 IDD - Supply current [mA] 42 36 30 24 18 12 6 0
IDD vs. fEX
(VDD = 3V, Topr = 25C, Typical)
Sleep mode (1/2 frequency dividing mode) Sleep mode (1/4 frequency dividing mode) Sleep mode (1/8 frequency dividing mode) Sleep mode (1/16 frequency dividing mode) 0 10 20 30 40 fEX - Main clock base oscillation frequency [MHz]
- 39 -
CXP973F064
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
- 40 -
CXP973F064
Package Outline
Unit: mm
100PIN LQFP (PLASTIC)
16.0 0.2 14.0 0.1 75 76 51 50
B
A
100 1 0.5 b 25
26
(0.22)
0.13 M
+ 0.2 1.5 - 0.1
0.1 0.1
+ 0.08 b = 0.18 - 0.03 ( 0.18 )
0.5 0.2
0 to 10
DETAIL B NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 P-LQFP100-14x14-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 0.7g
100PIN LQFP (PLASTIC)
16.0 0.2 14.0 0.1 75 76 51 50
(0.127)
+ 0.05 0.127 - 0.02
B
A
100 1 0.5 b 25
26
(0.22)
0.13 M
+ 0.2 1.5 - 0.1
0.1 0.1
+ 0.08 b = 0.18 - 0.03 ( 0.18 )
0.5 0.2
0 to 10
DETAIL B NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 P-LQFP100-14x14-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 0.7g
LEAD SPECIFICATIONS ITEM LEAD MATERIAL LEAD TREATMENT LEAD TREATMENT THICKNESS SPEC. ALLOY 42 Sn-Bi 2.5% 5-18m
- 41 -
(0.127)
+ 0.05 0.127 - 0.02
0.5 0.2
0.1
(15.0)
0.5 0.2
0.1
(15.0)
CXP973F064
Package Outline
Unit: mm
104PIN LFLGA
0.2
SA 11.0
1.4MAX PIN 1 INDEX X 0.01
11.0
x4 0.15 S
0.2
0.20 S
SB
0.8 N M L K J H G F E D C B A
DETAIL X A 103 - 0.40 0.05 0.08 M S A B
B
0.4 1.6
0.7
0.7
1 2 3 4 5 6 7 8 9 101 11213
0.8
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.3g
SONY CODE EIAJ CODE JEDEC CODE
LFLGA-104P-01 P-LFLGA104-11x11-0.8
TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS
0.10 S
1.6 0.4
- 42 -
Sony Corporation

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